View CY62256VLL-70SNXI_3473884.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

256k (32k x 8) static ram cy62256v cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05057 rev. *f revised july 25, 2006 features ? high speed ?70 ns ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive: ?40c to 125c ? low voltage range: ? 2.7v ? 3.6v ? low active power and standby power ? easy memory expansion with ce and oe features ? ttl-compatible inputs and outputs ? automatic power-down when deselected ? cmos for optimum speed/power ? available in a pb-free and non pb-free standard 28-pin narrow soic, 28-pin tsop-1 and 28-pin reverse tsop-1 packages functional description [1] the cy62256v family is compos ed of two high-performance cmos static ram?s organized as 32k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ) and active low output enable (oe ) and tri-state drivers. these devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. an active low write enable signal (we ) controls the writing/reading operation of the memory. when ce and we inputs are both low, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 14 ). reading the device is accomplished by selecting the device and enabling the outputs, ce and oe active low, while we remains inactive or high. under these conditions, the contents of the location addressed by the information on address pins are present on th e eight data input/output pins. the input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com. a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 column decoder row decoder sense amps inputbuffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 32k 8 arra y i/o 7 i/o 6 i/o 5 i/o 4 a 10 a 13 a 11 a 12 a a 14 a 1 0 logic block diagram [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 2 of 12 pin configurations product portfolio product v cc range (v) speed power dissipation operating, i cc (ma) standby, i sb2 ( a) range min. typ. [2] max. (ns) typ. [2] max. typ. [2] max. cy62256vll com?l/ind?l 2.7 3.0 3.6 70 11 30 0.1 5 automotive 130 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view narrow soic 12 13 25 28 27 26 gnd a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 5 i/o 0 i/o 1 i/o 2 ce oe a 0 i/o 3 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 3 4 20 21 7 6 8 9 oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 0 ce i/o 7 i/o 6 i/o 5 gnd i/o 2 i/o 1 i/o 4 i/o 0 a 14 a 10 a 11 a 13 a 12 i/o 3 tsop i top view (not to scale) reverse pinout 22 23 24 25 26 27 28 1 2 5 10 11 15 14 13 12 16 19 18 17 3 4 20 21 7 6 8 9 oe a 1 a 2 a 3 a 4 we v cc a 5 a 6 a 7 a 8 a 9 a 0 ce i/o 7 i/o 6 i/o 5 gnd i/o 2 i/o 1 i/o 4 i/o 0 a 14 a 10 a 11 a 13 a 12 i/o 3 tsop i top view (not to scale) pin definitions pin number type description 1?10, 21, 23?26 input a 0 ?a 14 . address inputs 11?13, 15?19 input/output i/o 0 ?i/o 7 . data lines. used as input or output lines depending on operation 27 input/control we . when selected low, a write is co nducted. when selected high, a read is conducted 20 input/control ce . when low, selects the chip. when high , deselects the chip 22 input/control oe . output enable. controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high , i/o pins are tri-stated, and act as input data pins 14 ground gnd . ground for the device 28 power supply v cc . power supply for the device note: 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c, and t aa = 70 ns. [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 3 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential (pin 28 to pin 14) ........................................... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [3] ....................................?0.5v to v cc + 0.5v dc input voltage [3] .................................?0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range device range ambient temperature (t a ) [4] v cc cy62256v commercial 0 c to +70 c 2.7v to 3.6v industrial ? 40 c to +85 c automotive ? 40 c to +125 c electrical characteristics over the operating range parameter description test conditions cy62256v-70 unit min. typ. [2] max. v oh output high voltage i oh = ? 1.0 ma v cc = 2.7v 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 v v ih input high voltage 2.2 v cc +0.3v v v il input low voltage ?0.5 0.8 v i ix input leakage current gnd < v in < v cc com?l, ind?l ?1 +1 a automotive ?10 +10 a i oz output leakage current gnd < v in < v cc , output disabled com?l, ind?l ?1 +1 a automotive ?10 +10 a i cc v cc operating supply current v cc = 3.6v, i out = 0 ma, f = f max = 1/t rc all ranges 11 30 ma i sb1 automatic ce power-down current? ttl inputs v cc = 3.6v, ce > v ih , v in > v ih or v in < v il , f = f max all ranges 100 300 a i sb2 automatic ce power-down current? cmos inputs v cc = 3.6v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v, f = 0 com?l 0.1 5 a ind?l 0.1 10 automotive 0.1 130 notes: 3. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 4. t a is the ?instant-on? case temperature. [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 4 of 12 capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ.) 6pf c out output capacitance 8 pf thermal resistance parameter description test co nditions soic tsopi rtsopi unit ja thermal resistance (junction to ambient) [6] still air, soldered on a 3 4.5 inch, 2-layer printed circuit board 68.45 87.62 87.62 c/w jc thermal resistance (junction to case) [5] 26.94 23.73 23.73 c/w ac test loads and waveforms parameter 3.3v units r1 1100 ohms r2 1500 ohms r th 645 ohms v th 1.750 volts data retention characteristics (over the operating range) parameter description conditions [6] min. typ. [2] max. unit v dr v cc for data retention 1.4 v i ccdr data retention current v cc = 1.4v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v com?l 0.1 3 a ind?l 0.1 6 auto 0.1 50 t cdr [6] chip deselect to data retention time 0ns t r [6] operation recovery time t rc ns v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% <5ns <5 ns output v th equivalent to: the venin equivalent all input pulses r1 r th data retention waveform notes: 5. tested initially and after any design or proc ess changes that may affect these parameters. 6. no input may exceed v cc + 0.3v. v cc(min) v cc(min) t cdr v dr > 1.4v data retention mode t r ce v cc [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 5 of 12 switching characteristics over the operating range [7] parameter description cy62256v-70 unit min. max. read cycle t rc read cycle time 70 ns t aa address to data valid 70 ns t oha data hold from address change 10 ns t ace ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low-z [8] 5ns t hzoe oe high to high-z [8, 9] 25 ns t lzce ce low to low-z [8] 10 ns t hzce ce high to high-z [8, 9] 25 ns t pu ce low to power-up 0 ns t pd ce high to power-down 70 ns write cycle [10, 11] t wc write cycle time 70 ns t sce ce low to write end 60 ns t aw address set-up to write end 60 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 50 ns t sd data set-up to write end 30 ns t hd data hold from write end 0 ns t hzwe we low to high-z [8, 9] 25 ns t lzwe we high to low-z [8] 10 ns notes: 7. test conditions assume signal transition time of 5 ns or less timing reference levels of v cc /2, input pulse levels of 0 to v cc , and output loading of the specified i ol /i oh and 50 pf load capacitance. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 10. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 11. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 6 of 12 switching waveforms read cycle no. 1 (address transition controlled) [12, 13] read cycle no. 2 (oe controlled) [13, 14] write cycle no. 1 (we controlled) [10, 15, 16] notes: 12. device is continuously selected. oe , ce = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. 15. data i/o is high impedance if oe = v ih . 16. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 17. during this period, the i/os are in output state and input signals should not be applied. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance icc isb high data out oe ce v cc supply current t hd t sd t pwe t sa t ha t aw t wc t hzoe data in valid note 17 data i/o address ce we oe [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 7 of 12 write cycle no. 2 (ce controlled) [10, 15, 16] write cycle no. 3 (we controlled, oe low) [11, 16] switching waveforms (continued) t wc t aw t sa t ha t hd t sd t sce data in valid we data i/o address ce t hd t sd t lzwe t sa t ha t aw t wc t hzwe data in valid note 17 data i/o address we ce [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 8 of 12 typical dc and ac characteristics 1.6 1.8 1.0 0.6 0.4 0.2 1.6 1.4 1.2 1.0 0.8 ? 55 25 125 ? 55 25 125 1.2 1.0 0.8 normalized t aa ?14 ?12 ?10 ?8 ?6 ?4 0.0 1.0 1.5 22.5 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature ( c) normalized supply current vs. ambient temperature ambient temperature ( c) output voltage (v) output source current vs. output voltage 0.8 1.5 1.0 0.5 1.65 2.1 2.6 3.1 3.6 normalized t supply voltage (v) normalized access time vs. supply voltage 6 4 2 0.0 1.0 2.0 3.0 output sink current (ma) 0 output voltage (v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 normalized i cc normalized i cc t a = 25 c 0.6 0.0 0 aa 2.5 2.0 t a = 25 c 1.4 ? 55 25 105 2.5 2.0 1.5 current vs. ambient temperature ambient temperature ( c) 1.0 0.5 0.0 ?0.5 i sb 3.0 standby i sb2 a v cc = 3.0v v cc = 2.5v v cc = 2. 5v v c c = 3 . 3v 1.6 1.8 2.0 2.4 2.8 3.2 3.6 1.4 1.2 v cc = 3.0v v cc = 2.5v 0.5 8 10 12 14 t a = 25 c t a = 25 c v cc = 2.5v v cc = 2.5 v [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 9 of 12 typical dc and ac characteristics (continued) 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 normalized i cc cycle frequency (mhz) normalized i cc vs.cycle time 0.0 1000 0.50 t a = 25 c v in = 0.5v 1 v cc = 3.0v t a = 25 c v cc = 3v truth table ce we oe inputs/outputs mode power h x x high-z deselect/power-down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high-z deselect, output disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 70 cy62256vll-70snc 51-85092 28-pin (300 -mil narrow body) snc commercial cy62256vll-70snxc 28-pin (300-m il narrow body) snc (pb-free) cy62256vll-70zc 51-85071 28-pin tsop i cy62256vll-70zxc 28-pin tsop i (pb-free) CY62256VLL-70SNXI 51-85092 28-pin (300-mil narrow body) snc (pb-free) industrial cy62256vll-70zi 51-85071 28-pin tsop i cy62256vll-70zxi 28-pin tsop i (pb-free) cy62256vll-70zri 51-85074 28-pin reverse tsop i cy62256vll-70zrxi 28-pin reverse tsop i (pb-free) cy62256vll-70sne 51-85092 28-pin (300-mil narrow body) snc automotive cy62256vll-70snxe 28-pin (300-m il narrow body) snc (pb-free) cy62256vll-70ze 51-85071 28-pin tsop i cy62256vll-70zxe 28-pin tsop i (pb-free) cy62256vll-70zre 51-85074 28-pin reverse tsop i cy62256vll-70zrxe 28-pin reverse tsop i (pb-free) please contact your local cypress sales r epresentative for availability of these parts [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 10 of 12 package diagrams 51-85092-*b 28-pin (300-mil) snc (narrow body) (51-85092) 28-pin thin small outline package type 1 (8 13.4 mm) (51-85071) 51-85071-*g [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 11 of 12 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagrams (continued) all product and company names mentio ned in this document are the tradema rks of their respective holders. 51-85074-*f 28-pin reverse thin small outline package type 1 (8 13.4 mm) (51-85074) [+] feedback [+] feedback
cy62256v document #: 38-05057 rev. *f page 12 of 12 document history page document title: cy62256v, 256k (32k x 8) static ram document number: 38-05057 rev. ecn no. issue date orig. of change description of change ** 107248 09/10/01 szv changed from spec number: 38-00519 to 38-05057 *a 111445 11/01/01 mgn removed obsolete parts. change to standard format *b 115229 05/23/02 gbi changed sn package diagram *c 116507 09/04/02 gbi added footnote 1 clarified i cc spec for v cc(typ) = 2.5v *d 239134 see ecn aju added automotive product information *e 344595 see ecn syt added pb-free packages on page# 10 *f 493277 see ecn vkn changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed part # cy62256v25ll from the product offering updated ordering information table [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY62256VLL-70SNXI

	To Download CY62256VLL-70SNXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .